XINU
ether.h
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1 /* ether.h */
2 
3 /* Ethernet packet format:
4 
5  +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
6  | Dest. MAC (6) | Src. MAC (6) |Type (2)| Data (46-1500)... |
7  +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
8 */
9 
10 #define ETH_ADDR_LEN 6 /* Length of Ethernet (MAC) address */
11 typedef unsigned char Eaddr[ETH_ADDR_LEN];/* a physical Ethernet address*/
12 
13 /* Ethernet packet header */
14 
15 struct etherPkt {
16  byte dst[ETH_ADDR_LEN]; /* Destination Mac address */
17  byte src[ETH_ADDR_LEN]; /* Source Mac address */
18  uint16 type; /* Ether type field */
19  byte data[1]; /* Packet payload */
20 };
21 
22 #define ETH_HDR_LEN 14 /* Length of Ethernet packet */
23  /* header */
24 
25 /* Ethernet DMA buffer sizes */
26 
27 #define ETH_MTU 1500 /* Maximum transmission unit */
28 #define ETH_VLAN_LEN 4 /* Length of Ethernet vlan tag */
29 #define ETH_CRC_LEN 4 /* Length of CRC on Ethernet */
30  /* frame */
31 
32 #define ETH_MAX_PKT_LEN ( ETH_HDR_LEN + ETH_VLAN_LEN + ETH_MTU )
33 
34 #define ETH_BUF_SIZE 1518 /* 1500 MTU + 14 ETH Header + 4 bytes optional VLAN Tagging */
35 
36 /* State of the Ethernet interface */
37 
38 #define ETH_STATE_FREE 0 /* control block is unused */
39 #define ETH_STATE_DOWN 1 /* interface is currently */
40  /* inactive */
41 #define ETH_STATE_UP 2 /* interface is currently active*/
42 
43 /* Ethernet device control functions */
44 
45 #define ETH_CTRL_GET_MAC 1 /* Get the MAC for this device */
46 
47 /* Ethernet multicast */
48 
49 #define ETH_NUM_MCAST 32 /* Max number of multicast addresses*/
50 
51 /* Ehternet NIC type */
52 
53 #define ETH_TYPE_3C905C 1
54 #define ETH_TYPE_E1000E 2
55 
56 #define ETH_PHY_CTLREG 0
57 #define ETH_PHY_STATREG 1
58 
59 #define ETH_PHY_CTLREG_RESET 0x8000
60 #define ETH_PHY_CTLREG_SM 0x2040 /* Speed Mask */
61 #define ETH_PHY_10M 0x0000
62 #define ETH_PHY_100M 0x2000
63 #define ETH_PHY_1000M 0x0040
64 #define ETH_PHY_CTLREG_FD 0x0100
65 
66 #define ETH_PHY_STATREG_LINK 0x0004
67 
68 struct ethcblk {
69  byte state; /* ETH_STATE_... as defined above */
70  struct dentry *phy; /* physical eth device for Tx DMA */
71  byte type; /* NIC type_... as defined above */
72 
73  /* Pointers to associated structures */
74 
75  struct dentry *dev; /* address in device switch table */
76  void *csr; /* addr.of control and status regs. */
77  uint32 pcidev; /* PCI device number */
78  uint32 iobase; /* I/O base from config */
79  uint32 flashbase; /* flash base from config */
80  uint32 membase; /* memory base for device from config */
81 
82  void *rxRing; /* ptr to array of recv ring descriptors*/
83  void *rxBufs; /* ptr to Rx packet buffers in memory */
84  uint32 rxHead; /* Index of current head of Rx ring */
85  uint32 rxTail; /* Index of current tail of Rx ring */
86  uint32 rxRingSize; /* size of Rx ring descriptor array */
87  uint32 rxIrq; /* Count of Rx interrupt requests */
88 
89  void *txRing; /* ptr to array of xmit ring descriptors*/
90  void *txBufs; /* ptr to Tx packet buffers in memory */
91  uint32 txHead; /* Index of current head of Tx ring */
92  uint32 txTail; /* Index of current tail of Tx ring */
93  uint32 txRingSize; /* size of Tx ring descriptor array */
94  uint32 txIrq; /* Count of Tx interrupt requests */
95 
96  byte devAddress[ETH_ADDR_LEN];/* MAC address */
97 
98  uint8 addrLen; /* Hardware address length */
99  uint16 mtu; /* Maximum transmission unit (payload) */
100 
101  uint32 errors; /* Number of Ethernet errors */
102  sid32 isem; /* Semaphore for Ethernet input */
103  sid32 osem; /* Semaphore for Ethernet output */
104  uint16 istart; /* Index of next packet in the ring */
105 
106  int16 inPool; /* Buffer pool ID for input buffers */
107  int16 outPool; /* Buffer pool ID for output buffers */
108 
109  int16 proms; /* nonzero => promiscuous mode */
110 
111  int16 ed_mcset; /* nonzero => multicast reception set */
112  int16 ed_mcc; /* count of multicast addresses */
113  Eaddr ed_mca[ETH_NUM_MCAST];/* array of multicast addrs */
114 };
115 
116 extern struct ethcblk ethertab[]; /* array of control blocks */
uint32 pcidev
Definition: ether.h:77
#define ETH_NUM_MCAST
Definition: ether.h:49
unsigned char byte
符号なし8ビット値(unsigned char)
Definition: kernel.h:7
void * rxRing
Definition: ether.h:82
uint32 txTail
Definition: ether.h:92
uint32 txHead
Definition: ether.h:91
int16 inPool
Definition: ether.h:106
byte dst[ETH_ADDR_LEN]
Definition: ether.h:16
uint8 addrLen
Definition: ether.h:98
unsigned char Eaddr[ETH_ADDR_LEN]
Definition: ether.h:11
Definition: ether.h:68
uint32 rxHead
Definition: ether.h:84
byte state
Definition: ether.h:69
uint16 istart
Definition: ether.h:104
uint32 errors
Definition: ether.h:101
unsigned char uint8
符号なし8ビット値(unsigned char)
Definition: kernel.h:9
void * txBufs
Definition: ether.h:90
byte src[ETH_ADDR_LEN]
Definition: ether.h:17
int16 proms
Definition: ether.h:109
Definition: conf.h:6
struct ethcblk ethertab[]
Definition: ethinit.c:7
uint32 rxIrq
Definition: ether.h:87
int16 ed_mcset
Definition: ether.h:111
struct dentry * phy
Definition: ether.h:70
uint32 flashbase
Definition: ether.h:79
uint32 txIrq
Definition: ether.h:94
short int16
符号あり16ビット整数(short)
Definition: kernel.h:13
uint16 mtu
Definition: ether.h:99
void * txRing
Definition: ether.h:89
unsigned short uint16
符号なし16ビット整数(unsigned short)
Definition: kernel.h:17
uint16 type
Definition: ether.h:18
int16 ed_mcc
Definition: ether.h:112
uint32 membase
Definition: ether.h:80
uint32 iobase
Definition: ether.h:78
void * rxBufs
Definition: ether.h:83
struct dentry * dev
Definition: ether.h:75
byte data[1]
Definition: ether.h:19
#define ETH_ADDR_LEN
Definition: ether.h:10
Definition: ether.h:15
unsigned int uint32
符号なし32ビット整数(unsigned int)
Definition: kernel.h:15
void * csr
Definition: ether.h:76
uint32 rxRingSize
Definition: ether.h:86
uint32 txRingSize
Definition: ether.h:93
sid32 isem
Definition: ether.h:102
byte type
Definition: ether.h:71
int32 sid32
セマフォID
Definition: kernel.h:22
uint32 rxTail
Definition: ether.h:85
int16 outPool
Definition: ether.h:107
sid32 osem
Definition: ether.h:103