XINU
Data Structures | Macros
uart.h File Reference
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Data Structures

struct  uart_csreg
 

Macros

#define dll   buffer /* divisor latch (low byte) */
 
#define dlm   ier /* divisor latch (high byte) */
 
#define fcr   iir /* FIFO control (when written) */
 
#define rbr   buffer /* receive buffer (when read) */
 
#define thr   buffer /* transmit hold (when written) */
 
#define UART0_PADRX_ADDR   0x44E10970
 
#define UART0_PADRX_MODE   0
 
#define UART0_PADTX_ADDR   0x44E10974
 
#define UART0_PADTX_MODE   0
 
#define UART1_CLKCTRL_ADDR   0x44e0006c
 
#define UART1_CLKCTRL_EN   0x00000002
 
#define UART1_PADRX_ADDR   0x44E10980
 
#define UART1_PADRX_MODE   0
 
#define UART1_PADTX_ADDR   0x44E10984
 
#define UART1_PADTX_MODE   0
 
#define UART_BAUD   115200 /* Default console baud rate. */
 
#define UART_DLL   26 /* value for low byte of divisor latch */
 
#define UART_DLM   0 /* value for high byte of divisor latch */
 
#define UART_FCR_EFIFO   0x01 /* Enable in and out hardware FIFOs */
 
#define UART_FCR_RRESET   0x02 /* Reset receiver FIFO */
 
#define UART_FCR_TRESET   0x04 /* Reset transmit FIFO */
 
#define UART_FCR_TRIG0   0x00 /* RCVR FIFO trigger level one char */
 
#define UART_FCR_TRIG1   0x40 /* RCVR FIFO trigger level 1/4 */
 
#define UART_FCR_TRIG2   0x80 /* RCVR FIFO trigger level 2/4 */
 
#define UART_FCR_TRIG3   0xC0 /* RCVR FIFO trigger level 3/4 */
 
#define UART_FIFO_SIZE   64 /* chars in UART onboard output FIFO */
 
#define UART_IER_ELSI   0x04 /* Recv line status interrupt mask */
 
#define UART_IER_EMSI   0x08 /* Modem status interrupt mask */
 
#define UART_IER_ERBFI   0x01 /* Received data interrupt mask */
 
#define UART_IER_ETBEI   0x02 /* Transmitter buffer empty interrupt */
 
#define UART_IIR_IDMASK   0x0E /* 3-bit field for interrupt ID */
 
#define UART_IIR_IRQ   0x01 /* Interrupt pending bit */
 
#define UART_IIR_MSC   0x00 /* Modem status change */
 
#define UART_IIR_RDA   0x04 /* Receiver data available */
 
#define UART_IIR_RLSI   0x06 /* Receiver line status interrupt */
 
#define UART_IIR_RTO   0x0C /* Receiver timed out */
 
#define UART_IIR_THRE   0x02 /* Transmitter holding register empty */
 
#define UART_LCR_8N1   0x03 /* 8 bits, no parity, 1 stop */
 
#define UART_LCR_DLAB   0x80 /* Divisor latch access bit */
 
#define UART_LSR   5 /* Input" Line Status Register */
 
#define UART_LSR_BI   0x10 /* Break interrupt indicator */
 
#define UART_LSR_DR   0x01 /* Data ready */
 
#define UART_LSR_TEMT   0x40 /* Transmitter empty */
 
#define UART_LSR_THRE   0x20 /* Transmit-hold-register empty */
 
#define UART_MCR_DTR   0x01 /* DTR complement */
 
#define UART_MCR_LOOP   0x10 /* Enable loopback test mode */
 
#define UART_MCR_OUT2   0x08 /* User-defined OUT2 */
 
#define UART_MCR_RTS   0x02 /* RTS complement */
 
#define UART_MDR1_13X   0x00000003
 
#define UART_MDR1_16X   0x00000000
 
#define UART_MDR1_16XAB   0x00000002
 
#define UART_OUT_IDLE   0x0016 /* determine if transmit idle */
 
#define UART_SYSC_SOFTRESET   0x00000002
 
#define UART_SYSS_RESETDONE   0x00000001
 
#define UART_TX   0 /* offset of transmit buffer */
 

Macro Definition Documentation

◆ dll

#define dll   buffer /* divisor latch (low byte) */

Definition at line 46 of file uart.h.

◆ dlm

#define dlm   ier /* divisor latch (high byte) */

Definition at line 47 of file uart.h.

◆ fcr

#define fcr   iir /* FIFO control (when written) */

Definition at line 45 of file uart.h.

◆ rbr

#define rbr   buffer /* receive buffer (when read) */

Definition at line 43 of file uart.h.

◆ thr

#define thr   buffer /* transmit hold (when written) */

Definition at line 44 of file uart.h.

◆ UART0_PADRX_ADDR

#define UART0_PADRX_ADDR   0x44E10970

Definition at line 126 of file uart.h.

Referenced by platinit().

◆ UART0_PADRX_MODE

#define UART0_PADRX_MODE   0

Definition at line 128 of file uart.h.

Referenced by platinit().

◆ UART0_PADTX_ADDR

#define UART0_PADTX_ADDR   0x44E10974

Definition at line 127 of file uart.h.

Referenced by platinit().

◆ UART0_PADTX_MODE

#define UART0_PADTX_MODE   0

Definition at line 129 of file uart.h.

Referenced by platinit().

◆ UART1_CLKCTRL_ADDR

#define UART1_CLKCTRL_ADDR   0x44e0006c

Definition at line 122 of file uart.h.

◆ UART1_CLKCTRL_EN

#define UART1_CLKCTRL_EN   0x00000002

Definition at line 123 of file uart.h.

◆ UART1_PADRX_ADDR

#define UART1_PADRX_ADDR   0x44E10980

Definition at line 130 of file uart.h.

◆ UART1_PADRX_MODE

#define UART1_PADRX_MODE   0

Definition at line 132 of file uart.h.

◆ UART1_PADTX_ADDR

#define UART1_PADTX_ADDR   0x44E10984

Definition at line 131 of file uart.h.

◆ UART1_PADTX_MODE

#define UART1_PADTX_MODE   0

Definition at line 133 of file uart.h.

◆ UART_BAUD

#define UART_BAUD   115200 /* Default console baud rate. */

Definition at line 3 of file uart.h.

◆ UART_DLL

#define UART_DLL   26 /* value for low byte of divisor latch */

Definition at line 53 of file uart.h.

Referenced by ttyinit().

◆ UART_DLM

#define UART_DLM   0 /* value for high byte of divisor latch */

Definition at line 55 of file uart.h.

Referenced by ttyinit().

◆ UART_FCR_EFIFO

#define UART_FCR_EFIFO   0x01 /* Enable in and out hardware FIFOs */

Definition at line 82 of file uart.h.

Referenced by ttyinit().

◆ UART_FCR_RRESET

#define UART_FCR_RRESET   0x02 /* Reset receiver FIFO */

Definition at line 83 of file uart.h.

Referenced by ttyinit().

◆ UART_FCR_TRESET

#define UART_FCR_TRESET   0x04 /* Reset transmit FIFO */

Definition at line 84 of file uart.h.

Referenced by ttyinit().

◆ UART_FCR_TRIG0

#define UART_FCR_TRIG0   0x00 /* RCVR FIFO trigger level one char */

Definition at line 85 of file uart.h.

◆ UART_FCR_TRIG1

#define UART_FCR_TRIG1   0x40 /* RCVR FIFO trigger level 1/4 */

Definition at line 86 of file uart.h.

◆ UART_FCR_TRIG2

#define UART_FCR_TRIG2   0x80 /* RCVR FIFO trigger level 2/4 */

Definition at line 87 of file uart.h.

Referenced by ttyinit().

◆ UART_FCR_TRIG3

#define UART_FCR_TRIG3   0xC0 /* RCVR FIFO trigger level 3/4 */

Definition at line 88 of file uart.h.

◆ UART_FIFO_SIZE

#define UART_FIFO_SIZE   64 /* chars in UART onboard output FIFO */

Definition at line 5 of file uart.h.

Referenced by ttyhandle_out().

◆ UART_IER_ELSI

#define UART_IER_ELSI   0x04 /* Recv line status interrupt mask */

Definition at line 67 of file uart.h.

◆ UART_IER_EMSI

#define UART_IER_EMSI   0x08 /* Modem status interrupt mask */

Definition at line 68 of file uart.h.

◆ UART_IER_ERBFI

#define UART_IER_ERBFI   0x01 /* Received data interrupt mask */

Definition at line 65 of file uart.h.

Referenced by ttykickout().

◆ UART_IER_ETBEI

#define UART_IER_ETBEI   0x02 /* Transmitter buffer empty interrupt */

Definition at line 66 of file uart.h.

Referenced by ttyhandle_out(), and ttykickout().

◆ UART_IIR_IDMASK

#define UART_IIR_IDMASK   0x0E /* 3-bit field for interrupt ID */

Definition at line 73 of file uart.h.

Referenced by ttyhandler().

◆ UART_IIR_IRQ

#define UART_IIR_IRQ   0x01 /* Interrupt pending bit */

Definition at line 72 of file uart.h.

Referenced by ttyhandler().

◆ UART_IIR_MSC

#define UART_IIR_MSC   0x00 /* Modem status change */

Definition at line 74 of file uart.h.

Referenced by ttyhandler().

◆ UART_IIR_RDA

#define UART_IIR_RDA   0x04 /* Receiver data available */

Definition at line 76 of file uart.h.

Referenced by ttyhandler().

◆ UART_IIR_RLSI

#define UART_IIR_RLSI   0x06 /* Receiver line status interrupt */

Definition at line 77 of file uart.h.

Referenced by ttyhandler().

◆ UART_IIR_RTO

#define UART_IIR_RTO   0x0C /* Receiver timed out */

Definition at line 78 of file uart.h.

Referenced by ttyhandler().

◆ UART_IIR_THRE

#define UART_IIR_THRE   0x02 /* Transmitter holding register empty */

Definition at line 75 of file uart.h.

Referenced by ttyhandler().

◆ UART_LCR_8N1

#define UART_LCR_8N1   0x03 /* 8 bits, no parity, 1 stop */

Definition at line 61 of file uart.h.

Referenced by ttyinit().

◆ UART_LCR_DLAB

#define UART_LCR_DLAB   0x80 /* Divisor latch access bit */

Definition at line 60 of file uart.h.

Referenced by ttyinit().

◆ UART_LSR

#define UART_LSR   5 /* Input" Line Status Register */

Definition at line 99 of file uart.h.

◆ UART_LSR_BI

#define UART_LSR_BI   0x10 /* Break interrupt indicator */

Definition at line 102 of file uart.h.

Referenced by ttyhandler().

◆ UART_LSR_DR

#define UART_LSR_DR   0x01 /* Data ready */

Definition at line 101 of file uart.h.

Referenced by kgetc(), and ttyhandler().

◆ UART_LSR_TEMT

#define UART_LSR_TEMT   0x40 /* Transmitter empty */

Definition at line 104 of file uart.h.

◆ UART_LSR_THRE

#define UART_LSR_THRE   0x20 /* Transmit-hold-register empty */

Definition at line 103 of file uart.h.

Referenced by kputc().

◆ UART_MCR_DTR

#define UART_MCR_DTR   0x01 /* DTR complement */

Definition at line 94 of file uart.h.

◆ UART_MCR_LOOP

#define UART_MCR_LOOP   0x10 /* Enable loopback test mode */

Definition at line 95 of file uart.h.

◆ UART_MCR_OUT2

#define UART_MCR_OUT2   0x08 /* User-defined OUT2 */

Definition at line 92 of file uart.h.

◆ UART_MCR_RTS

#define UART_MCR_RTS   0x02 /* RTS complement */

Definition at line 93 of file uart.h.

◆ UART_MDR1_13X

#define UART_MDR1_13X   0x00000003

Definition at line 111 of file uart.h.

◆ UART_MDR1_16X

#define UART_MDR1_16X   0x00000000

Definition at line 109 of file uart.h.

Referenced by ttyinit().

◆ UART_MDR1_16XAB

#define UART_MDR1_16XAB   0x00000002

Definition at line 110 of file uart.h.

◆ UART_OUT_IDLE

#define UART_OUT_IDLE   0x0016 /* determine if transmit idle */

Definition at line 4 of file uart.h.

◆ UART_SYSC_SOFTRESET

#define UART_SYSC_SOFTRESET   0x00000002

Definition at line 115 of file uart.h.

Referenced by platinit().

◆ UART_SYSS_RESETDONE

#define UART_SYSS_RESETDONE   0x00000001

Definition at line 119 of file uart.h.

Referenced by platinit().

◆ UART_TX

#define UART_TX   0 /* offset of transmit buffer */

Definition at line 106 of file uart.h.

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